`timescale 1ns / 1ps

module Mux4_8bit_tb;

	reg [1:0] sel;
	reg [7:0] in0, in1, in2, in3;
	wire [7:0] out;
	Mux4_8bit dut (
		.sel(sel),
		.in0(in0),
		.in1(in1),
		.in2(in2),
		.in3(in3),
		.out(out)
	);

	initial begin
		in0 = 8'b00001111;
		in1 = 8'b11110000;
		in2 = 8'b10101010;
		in3 = 8'b01010101;

		sel = 2'b00; #10;  // in0
		sel = 2'b01; #10;  //  in1
		sel = 2'b10; #10;  //  in2
		sel = 2'b11; #10;  //  in3

		$stop;
	end

endmodule
